JPS6325737B2 - - Google Patents
Info
- Publication number
- JPS6325737B2 JPS6325737B2 JP57013010A JP1301082A JPS6325737B2 JP S6325737 B2 JPS6325737 B2 JP S6325737B2 JP 57013010 A JP57013010 A JP 57013010A JP 1301082 A JP1301082 A JP 1301082A JP S6325737 B2 JPS6325737 B2 JP S6325737B2
- Authority
- JP
- Japan
- Prior art keywords
- address
- data
- clock
- processing circuit
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
- G06F13/423—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus with synchronous protocol
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Communication Control (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57013010A JPS58130651A (ja) | 1982-01-29 | 1982-01-29 | デ−タ受信方式 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57013010A JPS58130651A (ja) | 1982-01-29 | 1982-01-29 | デ−タ受信方式 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS58130651A JPS58130651A (ja) | 1983-08-04 |
JPS6325737B2 true JPS6325737B2 (en]) | 1988-05-26 |
Family
ID=11821196
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP57013010A Granted JPS58130651A (ja) | 1982-01-29 | 1982-01-29 | デ−タ受信方式 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58130651A (en]) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0221235U (en]) * | 1988-07-21 | 1990-02-13 | ||
JPH02101937U (en]) * | 1989-01-31 | 1990-08-14 | ||
JPH0354448U (en]) * | 1989-09-26 | 1991-05-27 | ||
WO2020194668A1 (ja) * | 2019-03-28 | 2020-10-01 | 三菱電機株式会社 | 梱包装置 |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60174954U (ja) * | 1984-04-25 | 1985-11-20 | クラリオン株式会社 | デ−タ処理方式 |
-
1982
- 1982-01-29 JP JP57013010A patent/JPS58130651A/ja active Granted
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0221235U (en]) * | 1988-07-21 | 1990-02-13 | ||
JPH02101937U (en]) * | 1989-01-31 | 1990-08-14 | ||
JPH0354448U (en]) * | 1989-09-26 | 1991-05-27 | ||
WO2020194668A1 (ja) * | 2019-03-28 | 2020-10-01 | 三菱電機株式会社 | 梱包装置 |
Also Published As
Publication number | Publication date |
---|---|
JPS58130651A (ja) | 1983-08-04 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP0185609B1 (en) | Coherent interface with wraparound receive and transmit memories | |
EP0135879B1 (en) | Interface circuit and method for connecting a memory controller with a synchronous or an asynchronous bus system | |
JP3171741B2 (ja) | データ転送レートを整合させるための回路 | |
EP0969384B1 (en) | Method and apparatus for processing information, and providing medium | |
JPS6325737B2 (en]) | ||
JPH0140432B2 (en]) | ||
JPS584468A (ja) | マイクロプロセツサシステム | |
EP1156421A2 (en) | CPU system with high-speed peripheral LSI circuit | |
JPH0583235A (ja) | 速度変換時のデータエラー防止方式 | |
CA2019586C (en) | Interface circuit for data transmission between a microprocessor system and a time-division-multiplexed system | |
KR100263670B1 (ko) | 직접 기억 장소 접근 컨트롤러 | |
JPS6061859A (ja) | マイクロコンピュ−タのデ−タ通信方式 | |
JPH11122275A (ja) | シリアル通信システム | |
JP2570900B2 (ja) | アクセス制御装置及びアクセス制御方法 | |
JPS5837725A (ja) | バスライン占有制御方式 | |
JPH09311811A (ja) | シングルポートram2方向アクセス回路 | |
JPH0525216B2 (en]) | ||
JPH02224015A (ja) | リングメモリバツフアのセンタリング待ち時間の抑圧回路 | |
JPH0521253B2 (en]) | ||
JPH0581445A (ja) | マイクロコンピユータlsi | |
JPH04310161A (ja) | データ読出回路 | |
JPS6242637A (ja) | 並列形フレ−ムバツフア回路 | |
JPH02105248A (ja) | ファーストイン・ファーストアウトメモリ利用の通信方式 | |
JPS5999522A (ja) | 入出力制御方式 | |
JPH0528109A (ja) | データ受信方式 |